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APW7055
Advanced PWM and Linear Power Controller
Features
* *
Operates from 5V input supply 2 Regulated Voltage are provided
General Description
The APW7055 provides the power control and protections for two output voltages on M/B DDR applications. It integrates one PWM controller , one source-sink linear controller(LC) for DDR source-sink purpose, as well as the monitor and protection functions into a single package. The PWM controller supplies the VMEM(2.5V) with a standard buck converter. The source-sink linear controller regulates VTT(1.25V) power for DDR Termination. Additional built-in over-voltage protection (OVP) will be started when the VMEM output is above 115% of the internal DAC setting(VDAC) . OVP function will shutdown the upper MOSFET and disable all output voltage . The PWM controller's over-current function monitors the output current by sensing the voltage drop across the upper MOSFET`s rDS(ON) , eliminating the need for a current sensing resistor .
- Standard Buck Switching Power for VMEM
(2.5V)
- Linear Controller with Source-Sink Regula
tion for VTT(1.25V)
* *
Simple Single-Loop Control Design
- Voltage-Mode PWM Control
Excellent Output Voltage Regulation
- VMEM Output : VMEM 1.5% Over Tem-per
ature
- VTT Output : 1/2 VIN 25mV Over Temperature
*
Fast Transient Response
- Built-in Feedback Compensation - Full 0% to 100% Duty Ratio * * *
Over-Voltage and Over-Current Fault Monitors Constant Frequency Operation(200kHz) 16 pins, SSOP Package
Pin Description
VCC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 BOOT UGATE PHASE PGND MEM1 MEM0 OCSET VSEN
Applications
* * *
M/B DDR Power Regulation AGP/PCI Graphics Power Regulation SSTL-2 Termination
SS SD SOURCE SINK FB VIN GND
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev.A.1 - Dec., 2001 1 www.anpec.com.tw
APW7055
Ordering Information
APW 7055
L e a d F re e C o d e H a n d lin g C o d e Tem p. R ange P ackage C ode V o lt a g e C o d e V o lt a g e C o d e A : 2 .4 0 ~ 2 .5 5 V B : 2 .6 0 ~ 2 .7 5 V C : 2 .8 0 ~ 2 .9 5 V D : 3 .0 0 ~ 3 .1 5 V P ackage C ode N : S S O P -1 6 Tem p. R ange C : 0 to 7 0 C H a n d lin g C o d e TU : Tube TR : Tape & Reel L e a d F re e C o d e L : L e a d F r e e D e v ic e B la n k : O r ig in a l D e v ic e
Block Diagram
VCC SS OCSET
VCC OCP 28 A
200uA PHASE BOOT
Power O n Reset
G a te C o n tro l
UG ATE PGND E .A
4 .5 V OVP SD 115%
PW M
VSEN
S o ft S ta rt a n d F a u lt L o g ic O s c illa t o r
SOURCE IN H IB IT
T h e rm a l P r o t e c t io n T T L D /A C o n v e rte r
M EM 0 M EM 1
V M EM FB S IN K
V TT C o n tro l
GND V TT 50%
V IN
Absolute Maximum Ratings
Symbol VCC VI , VO TA TJ TSTG TS Supply Voltage Input , Output or I/O Voltage Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Soldering Temperature
2
Parameter
Rating 15 GND -0.3 V to VCC +0.3 0 to 70 0 to 125 -65 to +150 300 ,10 seconds
Unit V V C C C C
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Copyright ANPEC Electronics Corp. Rev. A. Rev.A.1 - Dec., 2001
APW7055
Thermal Characteristics
Symbol R JA Parameter Thermal Resistance in Free Air SOIC SOIC (with 3in2 of Copper) Value 75 65 Unit C/W
Electrical Characteristics
1. Recommended operating conditions, Unless otherwise noted. 2. Refer to Block and Simplified Power System Diagrams , and Typical Application Schematic.
Symbol Supply Current ICC Nominal Supply Current Shutdown Supply Current Rising VCC Threshold V CC V OCSET V SD Oscillator F OSC Free Running Frequency 185 200 1.9 -1.5 2.0 0.8 -10mV 0.495VIN +10mV -10mV 0.505VIN +10mV 0.8 0.8 VCC=5V,VBOOT=9.5V, VUGATE=6V VCC=12V,VBOOT=9.5V, VUGATE=6V VCC=5V,VUGATE=1V R GATE UGATE Sink VCC=12V, VUGATE=6V
3
Parameter
Test Conditions
Min.
APW 7055 Typ. Max. 7 2.7 4.2 4.6
Unit
SD=0V, GATE Drive Open SD=5V Vocset=3V Vocset=3V 3.6
mA
Power-on Reset Falling VCC Threshold Rising V OC SET Threshold Shutdown Input High Voltage Shutdown Input Low Voltage 2.0 0.8 215 kHz V +1.5 % V V 1.26 V V
V OSC Ramp Am plitude PW M Controller Reference Voltage V DAC DAC Voltage Accuracy MEM 0-1 Input High Voltage MEM 0-1 Input Low Voltage Source-Sink Linear Controller V SOURCE Source Regulation Voltage V SINK ISource Sink Regulation Voltage Source Drive Current
V mA
ISINK Sink Drive Current PW M Controllers Gate Drivers
1 A 1 3 3 3.5
IUGATE
UGATE Source
Copyright ANPEC Electronics Corp. Rev. A. Rev.A.1 - Dec., 2001
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APW7055
Electrical Characteristics (Cont.)
1. Recommended operating conditions, Unless otherwise noted. 2. Refer to Block and Simplified Power System Diagrams , and Typical Application Schematic.
Symbol Protection VSEN O.V. trip point (VSEN/VDAC) VSEN O.V. Hysteresis IOCSET ISS Ocset Current Source Soft start Current Vocset=3V 170 VSEN Rising 115 2 200 28 230 120 % uA Parameter Test Conditions APW7055 Typ. Max. Unit
Min.
Functional Pin Description
VCC (Pin 1) Provide a +5V bias supply for the IC to this pin. This pin also provides the gate bias charge for the MOS FETs of the source-sink regulator. The voltage at th is pin is monitored for Power-On Reset (POR) purposes. SS (Pin 2) This pin provides the soft start for the standard buck converter and source-sink regulator. Connect a capacitor from this pin to ground.This capacitor, along with an internal 28uA current source,sets the soft-start interval of the converter and preventing the outputs from overshoot as well as limiting the input current . SD (Pin 3) The pin shuts down all the outputs. A TTL-compatible, logic level high signal applied at this pin immediately discharges the soft-start capacitor,disabling all the outputs.When IC re-enabled, the IC undergoes a new soft-start cycle.Left open, this pin is pulled low by an internal pull-down resistor,enabling operation. SOURCE (Pin 4) Connect the pin to the upper MOSFET gate drive of the source-sink regulator. This pin is used to drive the
Copyright ANPEC Electronics Corp. Rev. A. Rev.A.1 - Dec., 2001 4
upper external MOSFET as a source regulator. SINK (Pin 5) Connect the pin to the lower MOSFET gate drive of the source-sink regulator.This pin is used to drive the lower external MOSFET as a sink regulator. FB (Pin 6) Connect this pin to output of the source-sink regulator. This pin provide the voltage feedback path for source and sink regulators. This pin is internally connected to the negative input of the source controller, and also connected to the positive input of the sink controller. VIN (Pin 7) Connect this pin to a voltage source. Two voltages, above 0.5VIN, are generated by an internal resistor divider as the reference voltage of the source and sink controllers. The internal resistor divider provides an offset voltage to ensure higher sink regulation voltage and prevent an direct current path through the upper and lower MOSFETs, damaging the two MOSFETs. GND (Pin 8) Signal ground for the IC. All voltage levels are mea sured with respect to this pin voltage protection.
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APW7055
Functional Pin Description (Cont.)
VSEN (Pin 9) This pin is connected to the standard buck converter's output voltage to provide the voltage feedback path for PWM converter. The OVP(Over-Voltage-Protection) comparator circuit use this signal to monitor output voltage status for over-voltage protection. OCSET (Pin 10) Connect a resistor (ROCSET ) from this pin to the drain of the standard buck PWM converter's MOSFET. ROCSET, an internal 200mA current source (IOCSET ), and the MOSFET's on-resistance(rDS(ON)) set the converter's over-current (OC) trip point according to the following equation:
IO CSET x ROCSET rDS(ON)
PGND (Pin 13) This is the power ground connection.Tie this pin to the anode of the flywheel diode of the standard buck PWM converter's circuit. PHASE (Pin 14) Connect the PHASE pin to the standard buck PWM converter's MOSFET source.This pin is used to monitor the voltage drop across the MOSFET for over-cur rent protection. UGATE (Pin 15) Connect this pin to the MOSFET gate of the standard buck PWM converter.This pin provides the gate drive for the external MOSFET. BOOT (Pin 16) This pin provides bias voltage to the external MOSFET driver. A bootstrap circuit may be used to pump a boot voltage for enforcing the driving capability of the gate driver and improving the performance of the MOSFET.
IPEAK =
An over-current trip cycles the soft-start function . MEM0-1 (Pin 11-12) MEM0-1 are TTL-compatible logic level input pins of the 2-bits DAC.The status of these 2 pins set the internal reference voltage(VDAC) for the standard buck converter and also sets the OVP threshold voltage.Table 1 shows the DAC table voltage. Table 1 DAC Table APW7055 - A
APW7055 - B
Pin Name MEM1 MEM0 0 0 1 1 0 1 0 1
VMEM Voltage 2.40 2.45 2.50 2.55
Pin Name MEM1 MEM0 0 0 1 1 0 1 0 1
VMEM Voltage 2.60 2.65 2.70 2.75
Copyright ANPEC Electronics Corp. Rev. A. Rev.A.1 - Dec., 2001
5
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APW7055
Table 1 DAC Table APW7055 - C APW7055 - D
Pin Name MEM1 MEM0 0 0 1 1 0 1 0 1
VMEM Voltage 2.80 2.85 2.90 2.95
Pin Name MEM1 MEM0 0 0 1 1 0 1 0 1
VMEM Voltage 3.00 3.05 3.10 3.15
Simplified Power System Diagram
V MEM Q2 Q1 S ource -S ink LC PW M C ontroller V MEM D1
5V D U A L
V TT
Q3 A P W 7055
Copyright ANPEC Electronics Corp. Rev. A. Rev.A.1 - Dec., 2001
6
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APW7055
Typical Application Circuit
D4 1N 4 14 8 5 VS B R1 10 C1 1u F 16 U1 VCC R4 10 k R1 1 NC 7 C1 3 0 .1u F 1 +5 VD U A L C1 4 0 .1u F C6 2 00p F 10 15 14 R3 0 D5 C7 10 00 u F Q 2A A PM7 31 3 + + Q2 B A PM7 31 3 R1 2 4 SO U RCE P GN D V SEN 5 S IN K APW 705 5 J2 6 R8 NC FB MEM1 MEM0 12 11 3 4 2 1 13 9 R6 SP ARE 1k 1N 4 14 8 R2 1k Q1 A PM9 41 0 L2 4.7u H D1 B3 4 + C4 10 00 u F + C5 10 00 u F + C1 7 10 00 u F C1 0 1u F + C3 10 00 u F L1 2u H
VI N
VI N
O CSET U G ATE P H AS E
BO O T
V MEM
V MEM
+ VTT
R5 0
C8 10 00 u F
C1 2 10 00 u F
R7 0
SS
GN D
2 C1 1 0 .1u F
SD
3
Copyright ANPEC Electronics Corp. Rev. A. Rev.A.1 - Dec., 2001
8
7
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APW7055
Package Informaion
SSOP-16
D N
H
E
G A UG E P LA NE
123 A e B A1 L
1
Millimeters Dim A A1 B D E e H L N 1 Min. 1.350 0.10 0.20 3.75 5.75 0.4 0 Max. 1.75 0.25 0.30 4.05 6.25 1.27 8
Variations- D Variations SSOP-16 Min. 4.75 Max. 5.05 Dim A A1 B D E e H L N 1
Inches Min. 0.053 0.004 0.008 0.147 0.226 0.016 0 0.069 0.010 0.012 0.160 0.246 0.050 8
Variations- D Min. 0.187 Max. 0.199 SSOP-16
Max. Variations
See variations 0.625 TYP.
See variations 0.025 TYP.
See variations
See variations
Copyright ANPEC Electronics Corp. Rev. A. Rev.A.1 - Dec., 2001
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APW7055
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
TP
(IR/Convection or VPR Reflow)
tp C ritical Zone T L to T P
R am p-up
T e m p e ra tu re
TL T sm ax
tL
T sm in R am p-down ts Preheat
25
t 25 C to Peak
T im e
Classificatin Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Large Body Small Body Pb-Free Assembly Large Body Small Body 3C/second max. 150C 200C 60-180 seconds 3C/second max 217C 60-150 seconds 245 +0/-5C 250 +0/-5C 10-30 seconds 20-40 seconds
Average ramp-up rate 3C/second max. (TL to TP) Preheat - Temperature Min (Tsmin) 100C - Temperature Mix (Tsmax) 150C - Time (min to max)(ts) 60-120 seconds Tsmax to TL - Ramp-up Rate Tsmax to TL - Temperature(TL) 183C - Time (tL) 60-150 seconds Peak Temperature(Tp) 225 +0/-5C 240 +0/-5C Time within 5C of actual Peak 10-30 seconds 10-30 seconds Temperature(tp) Ramp-down Rate 6C/second max. 6 minutes max. Time 25C to Peak Temperature
Copyright ANPEC Electronics Corp. Rev. A. Rev.A.1 - Dec., 2001 9
6C/second max. 8 minutes max.
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Note: All temperatures refer to topside of the package. Measured on the body surface.
APW7055
Reliability test program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C , 5 SEC 1000 Hrs Bias @ 125 C 168 Hrs, 100 % RH , 121C -65C ~ 150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms , Itr > 100mA
Carrier Tape & Reel Dimensions
t P P1 D Po E
F W
Bo
Ao
Ko D1
T2
J C A B
T1
Application
A 6.95
B 5.4 T2 2.2
D0
D1
E 1.750.1 C1 130.3
F 5.50.05 C2 210.8
P0 4.00.1 T1 13.50.5
P1 8.00.1 T2 2.00.2
P2 2.00.05 C 801
1.550.05 1.550.1 W 12.00.3 W1 9.5
SSOP-16
T 0.30.05
(mm)
Copyright ANPEC Electronics Corp. Rev. A. Rev.A.1 - Dec., 2001 10 www.anpec.com.tw
APW7055
Cover Tape Dimensions
Application SOP- 16 Carrier Width 24 Cover Tape Width 21.3 Devices Per Reel 1000
Customer Service
Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
Copyright ANPEC Electronics Corp. Rev. A. Rev.A.1 - Dec., 2001
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